
library ieee;
use ieee.std_logic_1164.all;

entity counterModuleTb is
end entity counterModuleTb;

architecture RTL of counterModuleTb is

	signal inputIn, enIn, clkIn, clrIn, output : bit; 
	
	component counterModule is
		port (
			input, en, clr, clk: in bit;
			output : out bit
		);
	end component counterModule;

	for all : counterModule use entity work.counterModule(STRUCTURAL); 
	
begin

	COUNTER : counterModule port map (inputIn, enIn, clkIn, clrIn, output);

	clkIn <= not clkIn after 10 ns;

	tb : PROCESS
		
	begin
	

	
	enIn <= '0';
	clrIn <= '0';
	inputIn <= '0';
	clrIn <= '0';
	

	wait for 20 ns;
	enIn <= '1';
	inputIn <= '1';
	wait for 40 ns;
	clrIn <= '1';
	

	
	wait;
		
	end PROCESS;

end architecture RTL;

